Every credible QPU roadmap — American or Chinese — still has to solve the same physical problem: get more qubits onto a chip, keep them coherent, and package the result at wafer scale. That is the manufacturing bottleneck this domain names.
Architectures differ, but every lab is racing toward the same milestone: verified quantum advantage, then fault tolerance.
| Lab | Chip / Program | Qubits | Architecture | 2026–2027 Target |
|---|---|---|---|---|
| IBM | Nighthawk / Loon | 120 | Superconducting, qLDPC memory path | Quantum advantage by end-2026; Kookaburra module 2026, fault tolerance 2029 |
| Willow | 105 | Superconducting, below-threshold error correction | First verified below-threshold QEC; error-corrected system by 2029 | |
| Microsoft | Majorana 1 | 8 topological | Topological qubits (topoconductor material) | Path to scaled fault tolerance with lower error-correction overhead |
| Amazon | Ocelot QPU | — | Cat qubits, built-in error-bias suppression | Reduce error-correction hardware overhead up to 90% |
| China — USTC / Origin Quantum | Zuchongzhi 3.0 / Wukong-180 | 105–180 | Superconducting, domestic full-stack | Fidelity parity claims with Willow; fully domestic fabrication in response to export controls |
Sources: IBM Newsroom, Google Quantum AI, Microsoft Azure Quantum, CSIS, The Quantum Insider — see Policy Catalysts for full citations.
IBM's, Google's, and China's superconducting processors are built through thin-film deposition, lithography, etching, and Josephson-junction fabrication on standard wafer substrates — the same process discipline as advanced semiconductor manufacturing, with tighter purity and defect tolerances. Yield and packaging at the wafer level, not qubit design alone, is the binding constraint on scaling qubit count into the thousands.
Cerebras's Wafer-Scale Engine already proved the commercial logic of aggregating compute at the full-wafer level rather than dicing into individual chips — a 4-trillion-transistor, 900,000-core device manufactured as one piece. The QPU roadmap is converging on the identical manufacturing philosophy: more processing units surviving on a single wafer, packaged and cooled together, rather than singulated and re-assembled.
U.S. and allied export controls on cryogenics, control electronics, and fabrication tools have pushed Chinese quantum manufacturers toward fully domestic supply chains. Origin Quantum in particular emphasizes self-developed chips, measurement-and-control systems, and software — a parallel wafer-fabrication track running independent of the Western supply chain.
IBM Quantum Network, Azure Quantum, Amazon Braket, and Google Quantum AI already sell QPU access by the second. The infrastructure pattern is identical to the GPU-first "neocloud" build-out (CoreWeave, Nebius, Crusoe, Nscale) — specialized, high-density, purpose-built compute sold as a service, distinct from general hyperscaler cloud.
In 2016, "GPU" quietly stopped meaning "a chip for rendering graphics" and started meaning "the unit AI infrastructure is priced in." The same linguistic shift is underway for QPU — driven by federal policy, hyperscaler naming conventions, and a hardware race that is now front-page, not back-page, news.
CPU → GPU → TPU → QPU. Each transition minted category-defining domain value once the acronym left the lab and entered procurement conversations. QPU crossed that line with Amazon's Ocelot QPU naming and federal budget language in 2026.
QPUWafers.com extends an established WAFERS naming family — AIWafers, InferenceWafers, CPUWafers, GPUWafers — into the one compute category those names do not yet cover: quantum.
The name reads correctly to five distinct buyer types without explanation: quantum hardware labs, wafer foundries, neocloud operators, government-adjacent quantum initiatives, and AI infrastructure investors.